Fault tolerant arrays of cells are known. United Kingdom Patent No. 2021825B describes a two dimensional wafer-scale array of integrated circuits (ICs) such as shift registers combined to provide a parallel memory. The array is initially tested to identify faulty ICs, and an external control circuit ensures that the faulty ICs are not implemented. The testing requirement is time-consuming and therefore expensive. The need for a separate control circuit communicating with all ICs leads to loss of wafer area to connecting lines. Moreover, the control circuit is of a different type to that of the ICs, which complicates design and production.
U.S. Pat. No. 3,913,072 describes the formation of a fully operational one-dimensional or linear array of ICs from a partly faulty two-dimensional wafer-scale array. A viable IC is first selected and connections are made to a further viable IC selected from four nearest neighbours. IC testing is carried out from an offwafer source. The procedure is carried out until a chain of ICs of the required length is built up. The circuitry for IC testing, selection and connection is complex. Furthermore, the procedure is only capable of providing a one-dimensional array of ICs in series.